1. Field of the Invention
This invention relates to fabrication technique of a semiconductor device and more particularly, to fabrication technique which prevents the flow of bonding wires at the time of molding of a resin mold package. For example, the present invention relates to technique which will be effective when applied to a semiconductor integrated circuit device (which will be hereinafter referred to as "PGA.IC" from time to time) equipped with a pin grid array package in which an outer dimension of a pellet and the length of bonding wires are great, which has multiple pins and for which a low cost is requisite.
2. Description of the Prior Art
Generally, a PGA type package is employed when the number of pins is great, the outer dimension of a semiconductor pellet is great and the length of bonding wires is great. A multi-pin economical PGA.IC is described, for example, in "Nikkei Electronics Micro-Devices No. 2" published by Nikkei McGraw-Hill, Jun. 11, 1984, pp. 160-168. The fabrication method of this IC is as follows.
The fabrication method of this PGA.IC uses a base which is prepared by laminating and pressing a copper foil on both sides of a glass-reinforced plastic. Through-hole and plating treatment is applied to this base and leads are formed on the base by photoetching. A recess is defined at the center of the base and a semiconductor pellet (hereinafter referred to as the "pellet") is bonded to the bottom of the recess by an epoxy resin or an epoxy type silver (Ag) paste. Both ends of bonding wires are bonded and bridged between the inner portions of the leads and electrode pads of the pellet by a ultrasonic or thermo-ultrasonic bonding apparatus. If PGA.IC has a multi-pin structure in this case, the arch length of the bonding wires becomes relatively great. A potting resin is potted into the recess defined at the center of the base and this potting resin effects resin molding of the pellet, the leads and the wires inside the recess.